DM368 DM365 ARM PLL Frequencies

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Background

TI states only TI provided DM365 / DM368 PLL configurations are supported. The follow is a list of setting RidgeRun has collected. For those that use a 24 Mhz (as found on the leo368 board) were tested.

The RidgeRun DM368/DM365 Linux SDK supports a user configuration setting to allow you to select the desired clock frequencies.

Boot output

DM368 ARM 432 Mhz and DDR 340 Mhz using 24 Mhz oscillator

Configure PLL frequencies for normal DM368 usage.

UBL May 14 2013 12:48:46

U-Boot 2010.12-rc2 (May 14 2013 - 12:48:47)

Cores: ARM 432 MHz
DDR:   340 MHz

DM365 ARM 297 Mhz and DDR 270 Mhz using 24 Mhz oscillator

Configure PLL frequencies for normal DM365 usage.

UBL May 14 2013 21:45:34


U-Boot 2010.12-rc2 (May 14 2013 - 21:45:36)

Cores: ARM 297 MHz
DDR:   270 MHz


HD DM368 ARM 445 Mhz and DDR 351 Mhz using 24 Mhz oscillator

HD 720p / 1080i video clock 74.24 Mhz. Overclocking ARM and DDR.

UBL May 14 2013 23:09:27


U-Boot 2010.12-rc2 (May 14 2013 - 23:09:28)

Cores: ARM 446 MHz
DDR:   351 MHz

DM365 ARM 270 Mhz and DDR 216 Mhz using 24 Mhz oscillator

Power saving configuration.

UBL May 14 2013 23:12:52


U-Boot 2010.12-rc2 (May 14 2013 - 23:12:54)

Cores: ARM 270 MHz
DDR:   216 MHz


DM365 ARM 216 Mhz and DDR 173 Mhz using 24 Mhz oscillator

Power saving configuration.

U-Boot 2010.12-rc2 (May 14 2013 - 23:16:04)

Cores: ARM 270 MHz
DDR:   108 MHz

Odd, the DDR frequency is too low.