FPGA V4L2 PCIe Driver and Wrappers
V4L2 FPGA is an ecosystem with drivers and a High-Level Synthesis wrapper
(RidgeRun’s HLS Wrapper) to make Image Signal Processing IP Cores V4L2
compliant. This ecosystem allows the user to see the FPGA device as pairs of video
devices accessible by user-space applications.
How the V4L2 FPGA Ecosystem Works
Figure 1 - V4L2 FPGA product diagram
V4L2 FPGA drivers allow users to access the FPGA as userspace video devices, sending video buffers to the FPGA through the sink device and retrieving the processed buffer from the source device (see Figure 2).
Figure 2 - V4L2 FPGA data flow
V4L2 FPGA v0.8.8 allows users to communicate with FPGAs connected through:
PCIe: single stream
AXI: single stream
The number of streams can be extended on-demand. Please contact us to get more information about sponsorship and engineering hours.
RidgeRun HLS Wrapper
The RidgeRun HLS Wrapper wraps the code of an ISP algorithm to handle the communication protocols of the accelerator with the driver. It is in charge of creating the control and stream ports, and facilitating the most fundamental registers for an image processing application. Thus, the user doesn't have to put time into defining interfaces or reading complicated datasheets to make his/her accelerator V4L2 compliant, allowing them to focus all their energy on describing the ISP algorithm
FPGA ISP is a collection of libraries for Image Signal Processing accelerators based on the RidgeRun HLS Wrapper. Create your own higher throughput accelerators with modules optimized for V4L2 FPGA.
NOTE: Additional platforms may be supported. Contact us for additional information.
Suggested Support Bundles
+20 support hours: $3999
Required support hours may change depending on customer FPGA design
and project requirements. RidgeRun recommends discussing project details
to create a quote and a rough estimate. An NDA can be put before this discussion.